In many electronic systems, data is synchronously transferred within or between different circuits by aligning the data to a periodic clock signal. Typically, to send and/or receive data, a derived clock signal is generated from a main system reference clock signal. The derived clock signal has a fixed, well defined phase relation to the main system reference clock signal. The derived clock signal is typically generated by a delay locked loop (DLL).
DLLs may be used to align data output from circuits, such as memory circuits, to the clock signal of a host. For example, in a double data rate (DDRx) synchronous dynamic random access memory (SDRAM), the data (DQ) written to the SDRAM is sent 90° in advance of the corresponding data strobe (DQS) signal. The DQS signal has a fixed timing relation (tDQSS) to the command clock (CLK) signal. For a read of the SDRAM, the DQ and DQS signals are specified to be edge aligned with the CLK signal. Therefore, an internal clock signal within the SDRAM is generated that runs in advance of the CLK signal by an amount equal to the combined delay through the output buffers.
A DLL receives a clock signal from a host or another suitable circuit and delays the clock signal to provide an output signal to align output data to the clock signal. The DLL compensates for differences in timing between the circuit and the host. Typically, a DLL includes a variable delay line that is controlled by a phase detector using closed loop regulation. The phase detector compares a feedback signal to the clock signal and outputs a control signal to adjust the delay of the delay line to set the phase difference between the clock signal and the feedback signal to a desired value.
In one embodiment, the variable delay line includes a chain of delay elements. Each delay element is assumed to provide an equal delay such that the desired phase relation between the input clock signal and the output clock signal is selected by tapping the output of a delay element. In practice, however, the delay elements typically do not have equal delays due to on-chip variations, which results in a non uniform resolution along the chain of delay elements. For some applications, this non uniform resolution along the chain of delay elements leads to errors.
For these and other reasons, there is a need for the present invention.